1. Field of the Invention
The present invention relates to a comparing device and particularly to a chopper-type comparator which can operate with high resolution and at high speed, the number of components thereof being decreased.
2. Description of the Prior Art
FIG. 6 is a diagram showing an example of a structure of a conventional chopper-type comparator. First of all, the structure of this chopper-type comparator will be described. In FIG. 6, an input terminal 1 is connected to a coupling capacitor 5 through a transmission gate 3 and an input terminal 2 is connected to the coupling capacitor 5 through a transmission gate 4. A voltage to be compared Vin is applied to the input terminal 1 and a reference voltage Vref is applied to the input terminal 2. The reference numerals 14 and 15 indicate gate terminals of the transmission gate 3 and the reference numerals 16 and 17 indicate gate terminals of the transmission gate 4. Clock signals .phi. and .phi. and clock signals .phi. and .phi. set respectively in a non-overlapping manner are applied to the gate terminals 14 and 15 and the gate terminals 16 and 17, respectively. These clock signals .phi. and .phi. serve to control the transmission gates 3 and 4 so that the transmission gate 3 and the transmission gate 4 are turned on and off complementarily. The coupling capacitor 5 is connected to a CMOS inverter 6 as well as to a transmission gate 7. N1 is a node among the coupling capacitor 5, the CMOS inverter 6 and the transmission gate 7. The CMOS inverter 6 comprises a p-channel MOS field effect transistor (hereinafter referred to as the p-channel MOS FET) 61 and an n-channel MOS field effect transistor (hereinafter referred to as the n-channel MOS FET) 62. One electrode of the p-channel MOS FET 61 is connected to a power supply terminal 13 of voltage V.sub.DD and the other electrode thereof is connected to one electrode of the n-channel MOS FET 62. The other electrode of the n-channel MOS FET 62 is grounded. The reference numerals 18 and 19 indicate gate terminals of the transmission gate 7 and clock signals .phi. and .phi. are applied to these gate terminals. The transmission gate 7 is controlled by these clock signals .phi. and .phi. so that the transmission gate 7 is turned on and off in a manner complementary to the transmission gate 3. The output of the CMOS inverter 6 and the output of the transmission gate 7 are both connected to one electrode of a coupling capacitor 8. The other electrode of the coupling capacitor 8 is connected to the input of a CMOS inverter 9 as well as to the input of a transmission gate 10. N2 is a node among the coupling capacitor 8, the CMOS inverter 9 and the transmission gate 10. The CMOS inverter 9 comprises a p-channel MOS FET 91 and an n-channel MOS FET 92. One electrode of the p-channel MOS FET 91 is connected to the power supply terminal 13 at voltage V.sub.DD and the other electrode thereof is connected to one electrode of the n-channel MOS FET 92. The other electrode of the n-channel MOS FET 92 is grounded. The reference numerals 20 and 21 indicate gate terminals of a transmission gate 10, clock signals .phi. and .phi. being applied to these gate terminals 20 and 21 respectively. The transmission gate 10 is controlled by these clock signals .phi. and .phi. so that the transmission gate 10 is turned on and off in a manner complementary to the transmission gate 3. The output of the CMOS inverter 9 and the output of the transmission gate 10 are both connected to a CMOS inverter 11. The CMOS inverter 11 comprises a p-channel MOS FET 111 and an n-channel MOS FET 112. One electrode of the p-channel MOS FET 111 is connected to the power supply terminal 13 at the voltage V.sub.DD and the other electrode thereof is connected to one electrode of the n-channel MOS FET 112. The other electrode of the n-channel MOS FET 112 is grounded. The CMOS inverter 11 is connected to an output terminal 12. The voltage at the output terminal 12 of the CMOS inverter 11 is Vout.
FIG. 7 is a graph showing characteristics of the CMOS inverters 6, 9 and 11 in FIG. 6, the horizontal axis representing input voltage and the vertical axis representing output voltage. As shown by the characteristic curve .alpha., the CMOS inverters 6, 9 and 11 have the common characteristics. Taking the CMOS inverter 6 as an example, when the input voltage is 0, the p-channel MOS FET 61 is in the ON state and the n-channel MOS FET 62 is in the OFF state and accordingly the output voltage of the CMOS inverter 6 is V.sub.DD. When the input voltage is V.sub.DD, the p-channel MOS FET 61 is in the OFF state and the n-channel MOS FET 62 is in the ON state and accordingly the output voltage of the CMOS inverter 6 is 0. It is the same with the CMOS inverters 9 and 11. When the transmission gates 7 and 10 are in the ON state, the outputs of the CMOS inverters 6 and 9 are connected to the respective inputs thereof and consequently the input voltage of the CMOS inverters 6 and 9 is equal to the output voltage thereof. In other words, the respective CMOS inverters 6 and 9 are in a balanced state at a point b' of intersection between the line extending from the origin 0 at an angle of 45.degree. with respect to the horizontal axis and the characteristic curve, and thus, the input voltage and the output voltage both become Vbal.
Now, the operation of the above described chopper-type comparator will be described. When the clock signal .phi. is at the level H, the transmission gates 7 and 10 are in the ON state and the voltages at the nodes N1 and N2 are both Vbal as shown in FIG. 7. In that period, the transmission gate 4 is in the ON state and voltages Vref and Vbal are applied to the respective ends of the coupling capacitor 5. The voltage Vbal of the CMOS inverter 6 and the voltage Vbal of the CMOS inverter 9 are applied to the respective two ends of the coupling capacitor 8. In the period when the clock signal .phi. is at the level L, only the transmission gate 3 is in the ON state and the voltage to be compared Vin is applied to the left electrode of the coupling capacitor 5, and accordingly the potential at the node N1 changes from Vbal by an amount of (Vin-Vref) if the stray capacitance or the like is not taken into account. As is clear from FIG. 7, a minor change in the input voltage causes a relatively large change in the output voltage in the vicinity of the intersection point b' and this change in the output voltage affects the CMOS inverter 9 through the coupling capacitor 8 and as a result the output voltage thereof is changed considerably from Vbal. The change amount is further increased by the CMOS inverter 11 in the following manner: ##EQU1## and as a result the circuit shown in FIG. 6 operates as a comparator.
Thus, in the conventional CMOS chopper-type comparator as described above, the respective input and output of the CMOS inverters 6 and 9 are connected by the transmission gates 7 and 10 and for the purpose of enhancing resolution, the CMOS inverter 6, the input and the output of which are connected by the transmission gate 7, is provided and connected to the CMOS inverter 9 through the coupling capacitor 8, the input and the output of the CMOS inverter 9 being connected by the transmission gate 10. In such a manner, the number of components is necessarily increased and the use of the coupling capacitor 8 involves a disadvantage that a change in the voltage of the CMOS inverter 6 having the input and the output connected by the transmission gate 7 cannot be efficiently transmitted to the CMOS inverter 9 having the input and the output connected by transmission gate 10.